1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for electrically connecting a semiconductor chip to a package substrate.
2. Description of the Related Art
Many present day semiconductor chips are mounted to a package substrate that is, in-turn, mounted to another printed circuit board. A package substrate is typically larger in size than its companion chip. A package substrate serves several purposes. In one aspect, a package substrate provides a convenient interface between a typically small semiconductor chip and a normally much larger printed circuit board. In another aspect, a package substrate provides a mounting surface and conductive pathways for a variety of passive components, such as capacitors, that are useful for the operation of but cannot be easily incorporated into a semiconductor chip.
In order to serve as an interface between a semiconductor chip and a printed circuit board, a typical package substrate includes a collection of conductor lines that may be interspersed in several different layers of insulating material. A variety of schemes are used to link the substrate conductor lines to a printed circuit board. Pins, solder balls and land pads are examples of structures used to connect to a printed circuit board. Similarly, a variety of techniques are used to electrically connect a semiconductor chip to the conductor lines of a package substrate. Two such techniques are bond line connections and flip-chip solder bump connections.
In one conventional flip-chip solder bump design, a package substrate includes a mounting surface that is destined to receive a semiconductor chip. The mounting surface includes a collection of conductive bump pads and component pads. A solder mask is formed on the mounting surface and patterned lithographically with a series of openings that lead to the bump pads and the component pads. The openings leading to the bumps pads are patterned with a lateral dimension that is smaller than the lateral dimension of the bump pad. In one conventional design, the bump pads have a round footprint. In another conventional design, the bumps pads have a rectangular footprint. A solder stencil is next placed on the solder mask. The solder stencil has an array of openings that line up vertically with the collection of openings in the solder mask. Solder is pressed into the openings and the stencil is removed. To provide the solder structures present in the bump pad openings with an improved and consistent shape, a coining operation is performed. The coined solder structures are often referred to as a “pre-solders”. Conventional pre-solders are typically composed of low temperature melting point solders, such as tin-lead eutectics.
To interface with the pre-solders of the package substrate, the semiconductor chip is provided with a group of solder bumps. Some conventional chip solder bumps are composed of high lead content lead-tin solder. To form the solder bumps in such cases, a high lead content lead-tin solder is deposited on conductive bump pads of the semiconductor chip. The semiconductor chip (usually at the wafer stage) is next heated to a high enough temperature to reflow the solder bumps. The wafer is subsequently diced into individual chips. A given individual chip is seated on a package substrate so that the solder bumps of the chip are brought into contact with the pre-solders of the package substrate and a reflow is performed to merge the solder bumps and pre-forms into conductive pillars. The metallurgical bonding between the high lead content tin-lead solder bumps and the pre-solders is not the result of the melting and wetting of both the low melting point eutectic pre-solders and the high melting point solder bumps. Rather, the reflow is performed at a little above the melting point of the eutectic pre-solders but well below the melting point of the high lead content solder bumps such that the metallurgical bonding is due to pre-solder liquification and wetting to the solid phase solder bumps. Thus, by using eutectic pre-solders, the substrate need not be subjected to potentially damaging high temperatures that would be necessary to melt the high lead content tin-lead bumps.
The foregoing conventional pre-solder design has been successfully used on a number of package designs. However, the materials, tools and processing time required to form an array of pre-solders do represent cost items that add to the overall cost of producing a packaged semiconductor chip.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.